UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1183

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Mnemonic
OR
ORI
PREPARE
RETI
SAR
SASF
SATADD
SATSUB
SATSUBI
SATSUBR reg1,reg2
SETF
reg1,reg2
imm16,reg1,reg2
list12,imm5
list12,imm5,
sp/imm
reg1,reg2
imm5,reg2
cccc,reg2
reg1,reg2
imm5,reg2
reg1,reg2
imm16,reg1,reg2
cccc,reg2
Operand
Note 15
r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1]
r r rr r1 10 10 0 RRRRR
i i i i i i i i i i i i i i i i
0 0 0 0 0 1 1 1 1 0 i i i i i L
LLLLLLLLLLL00001
0 0 0 0 0 1 1 1 1 0 i i i i i L
L L L L L L L L L L L f f 0 1 1
imm16/imm32
0000011111100000
0000000101000000
r r rr r1 11 11 1 RRRRR
0000000010100000
r r r r r 0 1 0 1 0 1 i i i i i
r r r r r 1 1 1 1 1 1 0 c c c c
0000001000000000
r r rr r0 00 11 0 RRRRR GR[reg2]←saturated(GR[reg2]+GR[reg1])
r r r r r 0 1 0 0 0 1 i i i i i
r r rr r0 00 10 1 RRRRR GR[reg2]←saturated(GR[reg2]–GR[reg1])
r r rr r1 10 01 1 RRRRR
i i i i i i i i i i i i i i i i
r r rr r0 00 10 0 RRRRR GR[reg2]←saturated(GR[reg1]–GR[reg2])
r r r r r 1 1 1 1 1 1 0 c c c c
0000000000000000
Opcode
Note 16
APPENDIX C INSTRUCTION SET LIST
User’s Manual U18279EJ3V0UD
GR[reg2]←GR[reg1]OR zero-extend(imm16)
Store-memory(sp–4,GR[reg in list12],Word)
sp←sp–4
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend(imm5)
Store-memory(sp–4,GR[reg in list12],Word)
GR[reg in list 12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 step above until all regs in list12 is loaded
PC←GR[reg1]
if PSW.EP=1
then PC
else if PSW.NP=1
GR[reg2]←GR[reg2]arithmetically shift right
by GR[reg1]
GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend(imm5)
if conditions are satisfied
then GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000000H
GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
If conditions are satisfied
then GR[reg2]←00000001H
else GR[reg2]←00000000H
PSW ←EIPSW
then
else
←EIPC
PC
PSW ←FEPSW
PC
PSW ←EIPSW
←FEPC
←EIPC
Operation
Note 4
Note 4
Note 17
n+1
n+2
1
1
4
1
1
1
1
1
1
1
1
1
Execution
i
Clock
Note 4
Note 4
Note 17
n+1
n+2
1
1
4
1
1
1
1
1
1
1
1
1
r
Note 4
Note 4
Note 17
n+1
n+2
4
1
1
1
1
1
1
1
1
1
1
1
l
CY OV S
R
×
×
×
×
×
×
×
R
0
0
0
0
×
×
×
×
×
Flags
R
×
×
×
×
×
×
×
×
×
R
Z SAT
×
×
×
×
×
×
×
×
×
1181
(4/6)
R
×
×
×
×
×