UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 910

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.14
17.14.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0)
to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not
used.
is set after the bus is released (after a stop condition is detected).
release due to an interrupt request (INTIIC) occurrence (detecting a stop condition), and then writing the address to
the IIC0 register. Before detecting a stop condition, data written to the IIC0 register is set to invalid.
determined according to the bus status.
If the bus has been released ..................................................a start condition is generated
If the bus has not been released (standby mode) ..................communication reservation
then check the IICS0.MSTS0 bit.
settings for the IICX0.CLX0, IICCL0.SMC0, and IICCL0.CL00 bits.
908
To start master device communications when not currently using a bus, a communication reservation can be made
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
If the IICC0.STT0 bit is set (1) while the bus is not used, a start condition is automatically generated and wait status
A communication is automatically started as the master by setting the IICC0.SPIE0 bit to 1, detecting the bus
When the STT0 bit has been set (1), the operation mode (as start condition or as communication reservation) is
To detect which operation mode has been determined for the STT0 bit, set the STT0 bit (1), wait for the wait period,
Wait periods, which should be set via software, are listed in Table 17-6. These wait periods can be set via the
The communication reservation timing is shown below.
released when the IICC0.LREL0 bit was set to “1”).
Communication Reservation
f
f
f
f
f
f
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
/4 (IICOCKS = 10H)
/6 (IICOCKS = 11H)
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
/4 (IICOCKS = 10H)
/6 (IICOCKS = 11H)
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
/8 (IICOCKS = 12H)
/10 (IICOCKS = 13H)
Selection Clock
CLX0
0
0
0
0
0
0
0
0
0
0
1
1
Table 17-6. Wait Periods
User’s Manual U18279EJ3V0UD
SMC0
CHAPTER 17 I
0
0
0
0
0
0
1
1
1
1
1
1
CL00
0
0
1
1
1
1
x
x
x
x
x
x
2
C BUS
23 clocks
23 clocks
43 clocks
43 clocks
43 clocks
43 clocks
15 clocks
15 clocks
15 clocks
15 clocks
9 clocks
9 clocks
Wait Clock
2.88
3.59
2.69
4.03
5.38
6.72
0.94
1.41
1.88
2.34
1.13
1.41
When f
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
Wait Time
s
s
s
s
s
s
s
s
s
s
s
s
XX
= 64 MHz