UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 208

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

206
(6) TAAn option register 0 (TAAnOPT0)
Note With the V850E/IF3, this bit can be set only in TAA2 and TAA4. Be sure to set bits 4 and 5 of TAA0,
Cautions 1. Rewrite the TAAmCCS1 and TAAmCCS0 bits when the TAAmCE bit = 0. (The same value
The TAAnOPT0 register is an 8-bit register that sets the capture/compare operation and detects overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TAA1, and TAA3 to “0”.
With the V850E/IG3, this bit can be set only in TAA2 to TAA4. Be sure to set bits 4 and 5 of TAA0 and
TAA1 to “0”.
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
TAAnOPT0
V850E/IF3
n = 0 to 4
m = 2, 4
V850E/IG3
n = 0 to 4
m = 2 to 4
can be written when the TAAmCE bit = 1.) If rewriting was mistakenly performed, clear the
TAAmCE bit to 0 and then set the bits again.
After reset: 00H
TAAmCCS1
TAAmCCS0
The TAAmCCS1 bit setting is valid only in the free-running timer mode.
The TAAmCCS0 bit setting is valid only in the free-running timer mode.
Set (1)
Reset (0)
• The TAAnOVF bit is set to 1 when the 16-bit counter value overflows from FFFFH
• An overflow interrupt request signal (INTTAnOV) is generated at the same time
• The TAAnOVF bit is not cleared to 0 even when the TAAnOVF bit or the
• Before clearing the TAAnOVF bit to 0 after generation of the INTTAnOV signal,
• The TAAnOVF bit can be both read and written, but the TAAnOVF bit cannot be
to 0000H in the free-running timer mode or the pulse width measurement mode.
that the TAAnOVF bit is set to 1. The INTTAnOV signal is not generated in
modes other than the free-running timer mode and the pulse width measurement
mode.
TAAnOPT0 register are read when the TAAnOVF bit = 1.
be sure to confirm (by reading) that the TAAnOVF bit is set to 1.
set to 1 by software. Writing 1 has no effect on the operation of TAAn.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
1
0
1
7
0
TAAnOVF
Note
Note
Compare register selected
Capture register selected (cleared by TAAmCTL0.TAAmCE bit = 0)
Compare register selected
Capture register selected (cleared by TAAmCTL0.TAAmCE bit = 0)
R/W
6
0
User’s Manual U18279EJ3V0UD
Address:
TAAmCCS1
Overflow occurred
0 is written to TAAnOVF bit or TAAnCTL0.TAAnCE bit = 0
TAAmCCR1 register capture/compare selection
TAAmCCR0 register capture/compare selection
5
Note
TAAmCCS0
TAA0OPT0 FFFFF665H, TAA1OPT0 FFFFF685H,
TAA2OPT0 FFFFF6A5H, TAA3OPT0 FFFFFB05H,
TAA4OPT0 FFFFFB25H
TAAn overflow detection flag
4
Note
3
0
2
0
1
0
TAAnOVF
<0>