UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 932

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3 Memory Block Function
memory blocks of 2 MB and 2 MB. The bus width and programmable wait function can be independently specified for
each block.
18.3.1 Chip select control function
and CS1. The areas selected by CS0 and CS1 are fixed.
The allocation of memory blocks is described below.
930
The lower 4 MB of the 64 MB memory space is reserved for external memory expansion and is divided into
Of the 64 MB address space (linear), the lower 4 MB (0000000H to 03FFFFFH) has two chip select functions, CS0
The memory area can be effectively used by dividing it into memory blocks using the chip select control function.
Notes 1.
2.
3.
CS0
CS1
Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the on-chip peripheral I/O,
specify addresses FFFF000H to FFFFFFFH.
μ
μ
μ
μ
PD70F3453: 8 KB
PD70F3454: 12 KB
PD70F3453: 128 KB
PD70F3454: 256 KB
3 F F B F F F H
3 F F F F F F H
3 F F C 0 0 0 H
0 3 F F F F F H
0 1 F F F F F H
0 4 0 0 0 0 0 H
0 2 0 0 0 0 0 H
0 0 0 0 0 0 0 H
Chip Select Signal
Access prohibited
(16 KB)
(2 MB)
(2 MB)
CHAPTER 18 BUS CONTROL FUNCTION
CS1
CS0
User’s Manual U18279EJ3V0UD
0000000H to 01FFFFFH (2 MB)
0200000H to 03FFFFFH (2 MB)
On-chip peripheral I/O area (4 KB)
Internal RAM area (12 KB
External memory area
0 0 F F F F F H
Internal ROM area (1 MB
0 0 0 0 0 0 0 H
3 F F F F F F H
3 F F F 0 0 0 H
3 F F E F F F H
3 F F C 0 0 0 H
0 3 F F F F F H
0 1 0 0 0 0 0 H
Area
Note 3
Note 2
)
)
Note 1