UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 184

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

182
(5) Oscillation stabilization time select register (OSTS)
Cautions 1. The wait time does not include the time until the clock oscillation starts (“a” in the figure
Remark f
The OSTS register selects the oscillation stabilization time until the oscillation stabilizes after the STOP mode
is released by interrupt request.
This register can be read or written in 8-bit units.
Reset sets this register to 04H.
2. The default value of the OSTS register after reset is 04H. If an 8 MHz resonator is used,
3. Be sure to set bits 4 to 7 to “0”.
X
: Oscillation frequency
OSTS
After reset: 04H
below) following release of the STOP mode.
therefore, the oscillation stabilization time is about 2 ms. Half the oscillation stabilization
time is consumed by waiting for the lockup of PLL. Therefore, the actual stabilization time
of the resonator is about 1 ms.
oscillation stabilization time is secured during the active period of the reset signal. To
release the STOP mode by an interrupt input other than a reset signal (RESET pin input,
reset signal (LVIRES) generation by low-voltage detector (LVI), reset signal (POCRES)
generation by power-on-clear circuit (POC)), the oscillation stabilization time is
determined by the set value of the OSTS register. Therefore, set a time twice as long as
that required for the resonator to stabilize to the OSTS register (because half the
oscillation stabilization time is the stabilization time of PLL).
OSTS3
0
0
0
0
0
1
OSTS2
R/W
Other than above
Voltage waveform X2 pin
0
1
1
1
1
0
CHAPTER 5 CLOCK GENERATOR
Address: FFFFF6C0H
OSTS1
CV
User’s Manual U18279EJ3V0UD
0
0
1
1
0
DD
0
OSTS0
When releasing reset, therefore, make sure that the
mode release
0
1
0
1
0
0
STOP
OSTS3
2
2
2
2
2
Setting prohibited
a
14
15
16
17
18
/f
/f
/f
/f
/f
X
X
X
X
X
(2.05 ms)
(4.10 ms)
(8.19 ms)
(16.4 ms)
(32.8 ms)
stabilization time (f
Selection of oscillation
OSTS2
OSTS1
X
= 8 MHz)
OSTS0