UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1035

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.5 STOP Mode
21.5.1 Setting and operation status
mode.
functions is stopped.
are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate with an external clock continue operating.
the IDLE mode. When the external clock is not used, the power consumption can be minimized with only leakage
current flowing.
21.5.2 Releasing STOP mode
INTP07 (V850E/IG3 only), INTP08 to INTP13, INTP17, INTP18, INTADT0, or INTADT1 pin input), an unmasked
internal interrupt request signal (CSIB-related interrupt signal in the slave mode) from the peripheral functions
operable in the STOP mode, or a reset signal (RESET pin input, reset signal (LVIRES) generation by low-voltage
detector (LVI), or reset signal (POCRES) generation by power-on-clear circuit (POC)).
time has been secured.
The STOP mode is set by setting (1) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the STOP mode, the clock generator stops operation. Clock supply to the CPU and the on-chip peripheral
As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set
Table 21-7 shows the operation status in the STOP mode.
Because the STOP stops operation of the clock generator, it reduces the power consumption to a level lower than
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The STOP mode is released by an unmasked external interrupt request signal (INTP00, INTP01, INTP02 to
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization
(1) Releasing STOP mode by unmasked maskable interrupt request signal
The STOP mode is released by an unmasked maskable interrupt request signal, regardless of the priority of
the interrupt request. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request
that is issued later is serviced as follows.
Caution When PSC.INTM bit = 1, the STOP mode cannot be released by the unmasked maskable
(a) If an interrupt request with a priority lower than or same as the interrupt request currently being serviced is
(b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is
generated, the STOP mode is released, but the newly generated interrupt is not acknowledged. The
interrupt request itself is retained. Therefore, execution starts at the next instruction after the STOP
instruction.
issued, the STOP mode is released and that interrupt request is acknowledged. Therefore, execution
branches to the handler address.
set the STOP mode.
interrupt request signal.
CHAPTER 21 STANDBY FUNCTION
User’s Manual U18279EJ3V0UD
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