UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 874

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

872
(8) IIC shift register 0 (IIC0)
(9) Slave address register 0 (SVA0)
The IIC0 shift register is used for serial transmission/reception (shift operations) that is synchronized with the
serial clock.
The IIC0 shift register can be read or written in 8-bit units, but data should not be written to the IIC0 shift
register during a data transfer.
Access (read/write) the IIC0 shift register only during the wait period. Accessing this register in communication
states other than the wait period is prohibited. However, for the master device, the IIC0 shift register can be
written once only after the transmission trigger bit (IICC0.STT0 bit) has been set to 1.
When the IIC0 shift register is written during wait, the wait is cancelled and data transfer is started.
Reset sets this register to 00H.
The SVA0 register holds the I
However, rewriting this register is prohibited when the IICS0.STD0 bit = 1 (start condition detection).
The SVA0 register can be read or written in 8-bit units, but bit 0 is fixed to 0.
Reset sets this register to 00H.
After reset: 00H
After reset: 00H
SVA0
IIC0
7
7
R/W
R/W
6
6
2
C bus’s slave addresses.
Address: FFFFFD80H
Address: FFFFFD83H
User’s Manual U18279EJ3V0UD
5
5
CHAPTER 17 I
4
4
2
C BUS
3
3
2
2
1
1
0
0
0