UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 931

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.2 Bus Control Pins
18.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access
AD0 to AD15
A0 to A7
WAIT
CLKOUT
CS0, CS1
WR0, WR1
RD
ASTB
AD0 to AD15
WAIT
CLKOUT
CS0, CS1
WR0, WR1
RD
ASTB
Address bus
Data bus
External bus control signal
The pins used to connect an external device are listed in the table below.
The status of each pin is as follows when the internal ROM, internal RAM, and on-chip peripheral I/O is accessed.
Bus Control Pin
Bus Control Pin
Notes 1.
Access Destination
Table 18-1. Pin Status List In Internal ROM, Internal RAM, and On-Chip Peripheral I/O Access
2.
While the on-chip peripheral I/O is accessed, the address the on-chip peripheral I/O accesses is also
output to the external address bus.
The WAIT pin does not input any signal during this operation.
Table 18-2. Bus Control Pins (When Multiplexed Bus Mode Selected)
Table 18-1. Bus Control Pins (When Separate Bus Mode Selected)
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
I/O
I/O
I/O
I/O
Undefined
Hi-Z
Inactive
Data bus
Address bus
External wait control
External bus clock output
Chip select
Write strobe signal
Read strobe signal
Address strobe signal
Address/data bus
External wait control
External bus clock output
Chip select
Write strobe signal
Read strobe signal
Address strobe signal
Note 2
CHAPTER 18 BUS CONTROL FUNCTION
Internal ROM
Function
Function
User’s Manual U18279EJ3V0UD
Alternate-Function Pin
Alternate-Function Pin
Undefined
Hi-Z
Inactive
PDL0 to PDL15
P10 to P17
P44
P07
P34, P32
P46, P45
P47
P37
PDL0 to PDL15
P44
P07
P34, P32
P46, P45
P47
P37
Note 2
Internal RAM
Register to Switch Between Port Mode/
Register to Switch Between Port Mode/
PMCDL register
PMC1 register
PMC4 register
PMC0 register
PMC3 register
PMC4 register
PMC4 register
PMC3 register
PMC0 register
PMC3 register
PMC4 register
PMC3 register
PMCDL register
PMC4 register
PMC4 register
Alternate-Function Mode
Alternate-Function Mode
Note 1
Hi-Z
Inactive
On-Chip Peripheral I/O
Note 2
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