UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1186

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1184
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
13. i i i i i : Lower 5 bits of imm9.
14. In the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
22. Do not make a combination that satisfies all the following conditions when using the “MUL reg1, reg2,
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
r r r r r
RRRRR = reg2 specification
I I I I : Higher 4 bits of imm9.
(the higher 32 bits of the results are not written in the register), shortened by 1 clock.
reg3” instruction and “MULU reg1, reg2, reg3” instruction. Operation is not guaranteed when an
instruction that satisfies the following conditions is executed.
• Reg1 = reg3
• Reg1 ≠ reg2
• Reg1 ≠ r0
• Reg3 ≠ r0
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
= regID specification
APPENDIX C INSTRUCTION SET LIST
User’s Manual U18279EJ3V0UD