UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 179

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Oscillator
(2) IDLE control
(3) HALT control
(4) PLL
(5) Prescaler 1
(6) Prescaler 2
(7) Oscillation stabilization time wait control (OST)
(8) Clock monitor
The main resonator oscillates the following frequencies (f
• In PLL mode (×8 fixed): f
• In clock-through mode: f
All functions other than the oscillator, PLL, clock monitor operation, CSIB in slave mode, low-voltage detector
(LVI), and power-on-clear circuit (POC) are stopped.
Only the CPU clock (f
This circuit multiplies the clock generated by the oscillator (f
It operates in two modes: clock-through mode in which f
control register (PLLCTL), and PLL mode in which a multiplied clock is output.
This prescaler generates the clock (f
This circuit divides the system clock (f
The clock (f
This unit measures the time from when the clock generated by the oscillator was input until oscillation is
stabilized. It also counts the PLL lockup time.
The count clock can be selected from 2
The clock monitor samples the clock generated by the oscillator (f
When it detects stop of oscillation, output of the timer for motor control goes into a high-impedance state (for
details, see CHAPTER 10 MOTOR CONTROL FUNCTION).
XX
to f
XX
/8) to be supplied to the CPU clock (f
CPU
) is stopped.
X
X
= 4 to 8 MHz (f
= 4 to 8 MHz (f
CHAPTER 5 CLOCK GENERATOR
XX
XX
User’s Manual U18279EJ3V0UD
to f
14
).
/f
X
XX
XX
to 2
XX
/4096) to be supplied to on-chip peripheral functions.
= 4 to 8 MHz)
= 32 to 64 MHz)
18
/f
X
.
CPU
X
X
):
is output as is by setting the SELPLL bit of the PLL
) and internal system clock (f
X
) by 8.
X
), by using the internal oscillation clock.
CLK
) is generated.
177