UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 826

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

824
(2) Operation timing
Remark
SIBn pin capture
INTCBnR signal
CBnTSF bit
SCKBn pin
(1) Write 00H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E1H to the CBnCTL0 register, and select the transmission/reception mode and MSB first at the
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and
(5) When transmission/reception is started, output the serial clock to the SCKBn pin, output the transmit
(6) When transmission/reception of the transfer data length set with the CBnCTL2 register is completed,
(7) Read the CBnRX register.
(8) To continue transmission/reception, write the transmit data to the CBnTX register again.
(9) Read the CBnRX register.
(10) To end transmission/reception, write the CBnCTL0.CBnPWR bit = 0, the CBnCTL0.CBnTXE bit = 0,
SOBn pin
SIBn pin
timing
f
same time as enabling the operation of the communication clock (f
transmission/reception is started.
data to the SOBn pin in synchronization with the serial clock, and capture the receive data of the SIBn
pin.
stop the serial clock output, transmit data output, and data capturing, generate the reception end
interrupt request signal (INTCBnR) at the last edge of the serial clock, and clear the CBnTSF bit to 0.
and the CBnCTL0.CBnRXE bit = 0.
XX
n = 0 to 2
/4, and master mode.
(1)
(2)
(3)
(4)
(5)
Bit 7
Bit 7
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
User’s Manual U18279EJ3V0UD
Bit 1
Bit 1
(6)
(7)
Bit 0
Bit 0
(8)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
CCLK
Bit 4
Bit 4
).
Bit 3 Bit 2
Bit 3 Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
(9)
(10)
CCLK
) =