UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 751

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UARTB consists of the following hardware units.
(1) UARTB control register 0 (UBCTL0)
(2) UARTB status register (UBSTR)
(3) UARTB control register 2 (UBCTL2)
(4) UARTB FIFO control register 0 (UBFIC0)
(5) UARTB FIFO control register 1 (UBFIC1)
(6) UARTB FIFO control register 2 (UBFIC2)
This register controls the transfer operation of UARTB.
This register indicates the transfer status during transmission and the contents of a reception error. The
status flag of this register, which indicates the transfer status during transmission, indicates the data retention
status of the transmit shift register and the transmit data register (the UBTX register in the single mode or
transmit FIFO in the FIFO mode). Each reception error flag is set to 1 when a reception error occurs, and
cleared to 0 when 0 is written to the UBSTR register.
This register is used to specify the division ratio by which to control the baud rate (serial transfer speed) of
UARTB.
This register is used to select the operation mode of UARTB, clear the transmit FIFO/receive FIFO that
becomes valid in the FIFO mode, and specify the timing mode in which the transmission enable interrupt
request signal (INTUBTIT)/reception end interrupt request signal (INTUBTIR) occurs.
This register is valid in the FIFO mode. It generates a reception timeout interrupt request signal (INTUBTITO)
if data is stored in the receive FIFO when the next data does not come (start bit is not detected) even after
the reception wait time of the next data has elapsed after the stop bit has been received.
This register is valid in the FIFO mode. It is used to set the timing to generate the transmission enable
interrupt request signal (INTUBTIT)/reception end interrupt request signal (INTUBTIR), using the number of
data transmitted or received as a trigger.
Registers
Item
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Table 15-1. Configuration of UARTB
UARTB control register 0 (UBCTL0)
UARTB control register 2 (UBCTL2)
UARTB status register (UBSTR)
UARTB FIFO control register 0 (UBFIC0)
UARTB FIFO control register 1 (UBFIC1)
UARTB FIFO control register 2 (UBFIC2)
UARTB FIFO status register 0 (UBFIS0)
UARTB FIFO status register 1 (UBFIS1)
Receive shift register
UARTB receive data register AP (UBRXAP)
UARTB receive data register (UBRX)
Transmit shift register
UARTB transmit data register (UBTX)
User’s Manual U18279EJ3V0UD
Configuration
749