UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 983

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
19.11 Times Related to DMA Transfer
19.12 Cautions
<1> Response time to DMA request
<2> Memory access
The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below.
Notes 1. If an external interrupt (INTPn) is specified as the DMA transfer start factor, noise elimination time is
The minimum number of execution clocks during the DMA cycle in each mode is as follows.
(1) Memory boundary
(2) Transfer of misaligned data
(3) Bus arbitration for CPU
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
Block transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
Note One clock is always inserted between the read cycle and write cycle of DMA transfer.
The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
targets (internal RAM or on-chip peripheral I/O) during DMA transfer.
DMA transfer of 16-bit bus width misaligned data is not supported. If the source or the destination address is
set to an odd address, the LSB of the address is forcibly handled as “0”.
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the
CPU.
However, the CPU can access the internal ROM and RAM to/from which DMA transfer is not being executed.
• The CPU can access the internal ROM when DMA transfer is being executed between the on-chip
• The CPU can access the internal ROM and internal RAM when DMA transfer is being executed between on-
peripheral I/O and internal RAM.
chip peripheral I/Os.
2. Two clocks for the DMA cycle
added (n = 11 to 13, 15, 17, 18).
memory access (<2>)
memory access (<2>) × Number of transfers
Internal RAM access
On-chip peripheral I/O register access
Table 19-3. Number of Minimum Execution Clocks in DMA Cycle
DMA Cycle
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U18279EJ3V0UD
4 clocks
2 clocks
4 clocks + Number of wait cycles specified by VSWC register
Note 1
Note 2
Minimum Number of Execution Clocks
Note
Note
+ Transfer destination
+ Transfer destination
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