UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 882

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

generated depending on the setting of the IICC0.WTIM0 bit.
canceled and the transmitting side writes data to the IIC0 register to cancel the wait status.
880
A wait state is automatically generated after a start condition is generated. Moreover, a wait state is automatically
Normally, when the IICC0.WREL0 bit is set to 1 or when FFH is written to the IIC0 register, the wait status is
The master device can also cancel the wait status via either of the following methods.
• By setting the IICC0.STT0 bit to 1
• By setting the IICC0.SPT0 bit to 1
Transfer lines
Master
Slave
ACKE0
SDA
SCL
SCL
SCL
IIC0
IIC0
(b) When master and slave devices both have a nine-clock wait
Generated according to previously set ACKE0 bit value
H
(master: transmission, slave: reception, and ACKE0 = 1)
D2
6
6
D1
7
7
Figure 17-11. Wait State (2/2)
Master and slave both wait
after output of ninth clock.
User’s Manual U18279EJ3V0UD
D0
8
8
CHAPTER 17 I
ACK
9
9
from master
Wait state
and slave
2
C BUS
IIC0 data write (cancel wait)
1
Wait state
from slave
D7
FFH is written to IIC0 register or
WREL0 bit is set to 1.
1
D6
2
2
D5
3
3