UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 936

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5.3 Endian function
18.5.4 Bus width
16-bit, or 32-bit units. The following shows the operation for each type of access. All data is accessed in order
starting from the lower order side.
934
Byte data
Byte data
7
0
7
0
The
The
<1> Access to
<1> Access to
(1) Byte access (8 bits)
μ
μ
(a) When the data bus width is 16 bits
address (4n)
(b) When the data bus width is 8 bits
address (4n)
PD70F3454GC-8EA-A and 70F3454F1-DA9-A support little endian.
PD70F3454GC-8EA-A and 70F3454F1-DA9-A access on-chip peripheral I/O and external memory in 8-bit,
8-bit data is transmitted/received via a 16-bit bus. Therefore, if an even address is specified, the lower
byte of the external data bus address is accessed. If an odd address is specified, the higher byte of the
external data bus address is accessed.
8-bit data is transmitted/received via an 8-bit bus. Therefore, the specified even/odd address of the
external data bus is accessed.
15
External
data bus
7
0
External
data bus
8
7
0
Address
Address
4n
4n
Byte data
Byte data
7
0
7
0
<2> Access to
<2> Access to
address (4n + 1)
address (4n + 1)
CHAPTER 18 BUS CONTROL FUNCTION
15
External
data bus
8
7
0
External
data bus
7
0
User’s Manual U18279EJ3V0UD
Address
Address
4n + 1
4n + 1
Byte data
Byte data
7
0
7
0
<3> Access to
<3> Access to
address (4n + 2)
address (4n + 2)
15
External
data bus
External
data bus
8
7
0
7
0
Address
Address
4n + 2
4n + 2
Byte data
Byte data
7
0
7
0
<4> Access to
<4> Access to
address (4n + 3)
address (4n + 3)
15
External
data bus
External
data bus
8
7
0
7
0
Address
Address
4n + 3
4n + 3