UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 552

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

550
(3) TABn option register 2 (TABnOPT2)
Cautions 1. When using interrupt culling (the TABnOPT1.TABnID4 to TABnOPT1.TABnID0 bits are set to
The TABnOPT2 register is an 8-bit register that controls the timer Qn option function.
This register can be rewritten when the TABnCTL0.TABnCE bit is 1. However, rewriting the TABnDTM bit is
prohibited when the TABnCE bit is 1. The same value can be rewritten.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. To generate a dead time period, set a value 1 or greater to the TABnDTC register.
TABnOPT2
m = 1 to 3
n = 0, 1
other than 00000), be sure to set the TABnRDE bit to 1.
Therefore, the interrupt and transfer are generated at the same timing. The interrupt and
transfer cannot be set separately.
(TABnRDE bit = 0), transfer is not performed normally.
While the operation is stopped (TABnCTL0.TABnCE bit = 0), the dead time period is not
generated and the output levels of the TOBnT1 to TOBnT3 and TOBnB1 to TOBnB3 pins are
in the initial status. To protect the system, therefore, allow the TOBnT1 to TOBnT3 and
TOBnB1 to TOBnB3 pins go into a high-impedance state or select the port mode with
setting the output levels of the pins, before stopping the operation.
If the dead time period is not necessary, set the TABnDTC register to 0.
After reset: 00H
TABnDTM
TABnRDE
TABnRDE
Rewriting the TABnDTM bit is disabled during timer operation. If it is rewritten by
mistake, stop the timer operation by clearing the TABnCE bit to 0, and re-set the
TABnDTM bit.
<7>
0
1
0
1
CHAPTER 10 MOTOR CONTROL FUNCTION
TABnDTM TABnATM3 TABnATM2 TABnAT3 TABnAT2 TABnAT1 TABnAT0
Do not cull transfer (transfer timing is generated every time at crest
and valley).
Cull transfer at the same interval as interrupt culling set by the TABnOPT1
register.
Dead-time counter counts up normally and, if TOBnm output of TABn is
at a narrow interval (TOBnm output width < dead-time width), the dead-
time counter is cleared and counts up again.
Dead-time counter counts up normally and, if TOBnm output of TABn is
at a narrow interval (TOBnm output width < dead-time width), the dead-
time counter counts down and the dead-time control width is automatically
narrowed.
R/W
<6>
User’s Manual U18279EJ3V0UD
Address: TAB0OPT2 FFFFF601H, TAB1OPT2 FFFFF641H
<5>
Dead-time counter operation mode selection
<4>
If the interrupt and transfer are set separately
Transfer culling enable
<3>
<2>
<1>
<0>
(1/2)