UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 627

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) A/D converter n conversion time control register (ADnCTC)
Notes 1. The number of clocks (f
Cautions 1. See Table 12-2
The ADnCTC register is a register that specifies the number of A/D conversion clocks and A/D conversion time.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. Set the A/D conversion time in a range of 2 to 7.42
ADnFR3
2. Set the ADnFR3 to ADnFR0 bits when the ADnSCM.ADnCE bit = 0 (conversion operation is
3. Be sure to set bits 4 to 7 to “0”.
The number of clocks (f
(repeat), multiple channel conversion, or multiple channel conversion (repeat)) is the same.
A/D Conversion time = 1/f
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(n = 0, 1)
ADnCTC
ADnFR3 to ADnFR0 bits.
stopped).
After reset: 00H
Table 12-2. Number of A/D Conversion Clocks and A/D Conversion Time
ADnFR2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
ADnFR1
R/W
Number of A/D Conversion Clocks and A/D Conversion Time for the
AD01
CHAPTER 12 A/D CONVERTERS 0 AND 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AD01
0
AD01
Address: AD0CTC FFFFF222H, AD1CTC FFFFF2A2H
) from the start to the end of A/D conversion.
) per conversion during successive conversion (1-channel conversion
× Number of A/D conversion clocks
ADnFR0
User’s Manual U18279EJ3V0UD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
89
88
57
56
41
40
35
34
34
33
33
32
32
31
31
30
Number of A/D
0
Conversion
Clocks
μ
ADnFR3 ADnFR2 ADnFR1 ADnFR0
Note 1
s.
5.56
5.50
3.56
3.50
2.56
2.50
2.19
2.13
2.13
2.06
2.06
2.00
2.00
Setting prohibited
Setting prohibited
Setting prohibited
f
(f
AD01
XX
A/D Conversion Time (
= 64 MHz)
= 16 MHz
7.42
7.33
4.75
4.67
3.42
3.33
2.92
2.83
2.83
2.75
2.75
2.67
2.67
2.58
2.58
2.50
f
(f
AD01
XX
= 48 MHz)
= 12 MHz
μ
s)
Note 2
625