UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1187

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

D.1 Major Revisions in This Edition
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Page
Deletion of description in 5.3 (6) Clock monitor mode register (CLM)
Modification of description in Figure 10-6 Timing Chart of 6-Phase PWM Output Mode
Modification of description in Figure 10-21 Timing of Reflecting Rewritten Value
Modification of description in 10.4.5 (3) When not tuning TAAn
Addition of description to 11.3 (1) Watchdog timer mode register (WDTM)
Deletion of description in 11.4 Operation
Modification of description in Figure 12-3 Block Diagram of Operational Amplifier for Input Level
Amplification and Overvoltage Detection Comparator in A/D Converter 0
Modification of description in Figure 12-4 Block Diagram of Operational Amplifier for Input Level
Amplification and Overvoltage Detection Comparator in A/D Converter 1
Addition of Figure 12-5 CMPnCTL3 Register Selector Circuit Configuration
Modification of description in 12.3 (1) A/D converter n scan mode register (ADnSCM)
Addition of description to 12.3 (16) Operational amplifier n control register 0 (OPnCTL0)
Modification of description in 12.3 (17) Comparator n control register 0 (CMPnCTL0)
Modification of description in 12.5 Internal Equivalent Circuit
Modification of description in Figure 13-12 Processing of Analog Input Pin
Modification of figure in Figure 16-4 Block Diagram of CSIBn
Modification of description in 17.15 (4) Procedure for starting or stopping I
Addition of description to 18.6.3 Relationship between programmable wait and external wait
Modification of description in Figure 18-1 Example of Inserting Wait States
Addition of description to 19.12 (3) Bus arbitration for CPU
Modification of description in 22.2 (1) Reset source flag register (RESF)
Deletion of description in 22.3 (3) Reset operation (LVIRES) by low-voltage detector (LVI)
Deletion of description in 22.3 (4) Reset operation (POCRES) by power-on-clear circuit (POC)
Modification of description in 23.3 (1) Low-voltage detection register (LVIM)
Modification of description in 23.4.1 To use for internal reset signal
Modification of description in 23.4.2 To use for interrupt
Modification of description in 26.1.4 Cautions
Modification of description in 26.3.2 Setting
Addition of 27.2 Memory Configuration
Addition of description to 27.3 Functional Overview
Modification of description in 27.9 Rewriting by Self Programming
Modification of description in CHAPTER 29 PACKAGE DRAWINGS
APPENDIX D REVISION HISTORY
User’s Manual U18279EJ3V0UD
Description
2
C operation
1185