UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 133

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.5
Port 4 can be set to the input or output mode in 1-bit units.
Port 4 has an alternate function as the following pins.
Notes 1. Software pull-up function
Remark
Port 4
P40
P41
P42
P43
P44
P45
P46
P47
Pin Name
2. V850E/IG3 only
3. The P41 and P42 pins also function as on-chip debug pins. The on-chip debug function or port function
4.
IF3: V850E/IF3
IG3: V850E/IG3
GC (V850E/IF3): 80-pin plastic LQFP (14 × 14)
GC (V850E/IG3): 100-pin plastic LQFP (fine pitch) (14 × 14)
GF (V850E/IG3): 100-pin plastic LQFP (14 × 20)
F1 (V850E/IG3): 161-pin plastic FBGA (10 × 10)
(including the alternate functions) can be selected by using the level of the DRST pin, as shown in the
table below.
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only
P41/SOB0/TXDA0
P42/SCKB0/INTP13
Low-Level Input to DRST Pin
GC
IF3
38
39
40
41
42
43
44
45
GC
47
48
49
50
51
52
53
54
Pin No.
IG3
GF
75
76
77
78
79
80
81
82
Table 4-10. Alternate-Function Pins of Port 4
M14 SCKB0/INTP13/DDI
M13 TECR1/TIT10/TOT10/INTP14
P12 SIB0/RXDA0
N12 SOB0/TXDA0/DCK
K14 TOA41/TIA41/INTP18/RD
L14 TENC10/EVTT1/INTP15/WAIT
L13 TENC11/TIT11/TOT11/INTP16/WR1
L12 TOA40/TIA40/INTP17/WR0
F1
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18279EJ3V0UD
Port 4 Functions
Alternate-Function Pin Name
DCK
DDI
High-Level Input to DRST Pin
Notes 2, 3
Notes 2, 3
Note 4
Note 4
Note 4
Note 4
Input
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
Provided
Pull-Up
Note 1
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