UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 917

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.16.2 Master operation in multimaster system
Note Confirm that the bus release status (IICCL0.CLD0 bit = 1, IICCL0.DAD0 bit = 1) has been maintained for
1
No
a certain period (1 frame, for example). When the SDA pin is constantly low level, determine whether to
release the I
communication.
ACKE0 = WTIM0 = SPIE0 = 1
Set STCEN0, IICRSV0 = 0
Confirm bus status
reservation enable
Master operation
INTIIC interrupt
Communication
IICCL0 ← XXH
SVA0 ← XXH
IICC0 ← XXH
IICRSV0 = 0?
IICX0 ← 0XH
IICF0 ← 0XH
SPD0 = 1?
occurred?
SPIE0 = 1
IICE0 = 1
Set ports
started?
START
A
Yes
Yes
Yes
Yes
(communication start
request issued)
• Waiting for slave specification from another master
• Waiting for communication start request (depending on user program)
2
Confirmation of bus
status is in progress
C bus (SCL, SDA pins = high level) by referring to the specifications of the product in
Figure 17-17. Master Operation in Multimaster System (1/3)
Note
reservation disable
Communication
(no communication start request)
Bus release status for a certain period
No
No
No
See Table 4-14 Settings When Port Pins Are Used for Alternate Functions
to set the I
Transfer clock selection
Local address setting
Start condition setting
Slave operation
B
2
C mode before this function is used.
User’s Manual U18279EJ3V0UD
STCEN0 = 1?
CHAPTER 17 I
Yes
INTIIC interrupt
Slave operation
SPIE0 = 0
occurred?
Yes
No
2
C BUS
Waiting for communication request
No
INTIIC interrupt
SPD0 = 1?
SPT0 = 1
occurred?
Yes
Yes
No
No
Communication start preparation
(stop condition generation)
Waiting for stop condition
detection
Slave operation
915