UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 784

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

782
Figure 15-6. Timing of Asynchronous Serial Interface Reception End Interrupt Request Signal (INTUBTIR)
Receive data register
Cautions 1. Be sure to read all the data (the number of data indicated by the UBFIS0.UBRB4 to
INTUBTIR
(b) Reception timeout interrupt request signal (INTUBTITO) (only in FIFO mode)
RXDB (input)
When the timeout counter function (UBFIC1.UBTCE bit = 1) is used in the FIFO mode, the reception
timeout interrupt request signal (INTUBTITO) occurs if the next data does not come even after the next
data reception wait time specified by the UBFIC1.UBTC4 to UBFIC1.UBTC0 bits has elapsed and if data
is stored in receive FIFO.
The INTUBTITO signal does not occur while reception is disabled.
If as many receive data as the number set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits
are not received, the timing of reading less receive data than the specified number can be set by the
INTUBTITO signal.
Since the timeout counter starts counting at start bit detection, a receive timeout interrupt request signal
does not occur if data of 1 character has not been received.
2. Data is always received with one stop bit (1).
(output)
UBFIS0.UBRB0 bits) stored in the receive data register (UBRX register in the single
mode or receive FIFO in the FIFO mode (UBRXAP register)) even when a reception error
occurs.
Unless the receive data register is read, an overrun error occurs when the next data is
received, causing the reception error status to persist.
If the pending mode is specified in the FIFO mode, however, be sure to clear the FIFO
(UBFIC0.UBRFC bit = 1) after reading the data stored in receive FIFO.
In the FIFO mode, the FIFO can be cleared even without reading the data stored in
receive FIFO.
If a parity error or framing error occurs in the FIFO mode, the UBRXAP register can be
read in 16-bit (halfword) units.
A second stop bit is ignored.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Start
User’s Manual U18279EJ3V0UD
D0
D1
D2
D6
D7
Parity
Stop