UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 42

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

40
(e) Interrupt controller (INTC)
(f) Clock generator (CG)
(g) Timer/counter
(h) Watchdog timer (WDT)
(i) Serial interface
(j) A/D converter (ADC)
(k) On-chip debug function
This controller handles hardware interrupt requests (INTP00 to INTP18, INTADT0, INTADT1) from on-chip
peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these
interrupt requests, and multiple-interrupt servicing control can be performed.
The clock generator includes two basic operation modes: PLL mode (fixed to multiplication by eight) and
clock-through mode. It generates four types of clocks (f
the operating clock for the CPU (f
The V850E/IG3 incorporates four 16-bit interval timer M (TMM) channels, five 16-bit timer/event counter
AA (TAA) channels, two 16-bit timer/event counter AB (TAB) channels, and two 16-bit timer/event counter
T (TMT) channels, and can measure pulse interval widths or frequency, enable an inverter function for
motor control, and output a programmable pulse.
A watchdog timer is equipped to detect program loops, system abnormalities, etc.
It generates a non-maskable interrupt request signal (INTWDT) or internal reset signal (WDTRES) after an
overflow occurs.
The V850E/IG3 incorporates eight serial interface channels: for three asynchronous serial interface A
(UARTA) channels, one asynchronous serial interface B (UARTB) channel, three clocked serial interface B
(CSIB) channels, and one I
UART2 and CSIB1, and UARTB and CSIB2 share a pin.
For UARTA, data is transferred via the TXDAn and RXDAn pins (n = 0 to 2).
For UARTB, data is transferred via the TXDB and RXDB pins.
For CSIB, data is transferred via the SOBn, SIBn, and SCKBn pins (n = 0 to 2).
For I
One channel is provided for each of the high-speed, high-resolution 12-bit A/D converters (ADC0, ADC1)
(total of two channels), which have five analog input pins respectively, and one channel is provided for the
10-bit A/D converter (ADC2), which has eight analog input pins.
Both one of the ADC0 channels and three of the ADC1 channels include an operational amplifier and a
comparator so that these A/D converters can amplify an analog input voltage and detect overvoltage input.
An on-chip debug function supporting MINICUBE and MINICUBE2 can be used, so that a simple,
inexpensive debug environment can be organized.
2
C, data is transferred via the SCL and SDA pins.
2
C bus interface (I
CHAPTER 1 INTRODUCTION
CPU
User’s Manual U18279EJ3V0UD
).
2
C) channel. Of these, UART0 and CSIB0, UARTA1 and I
XX
, f
XX
/2, f
XX
/4, f
XX
/8), and supplies one of them as
2
C,