UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 601

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.5 TAAn tuning operation for A/D conversion start trigger signal output
a slave. The conversion start trigger signal of A/D converters 0 and 1 can be set as the A/D conversion start trigger
source by the INTTAnCC0 and INTTAnCC1 signals of TAAn and the INTTBnOV and INTTBnCC0 signals of TABn.
This section explains the tuning operation of TAAn and TABn in the 6-phase PWM output mode.
In the 6-phase PWM output mode, the tuning operation is performed with TABn serving as the master and TAAn as
Remark
(1) Tuning operation starting procedure
The TAAn and TABn registers should be set using the following procedure to perform the tuning operation.
(a) Setting of TAAn register (stop the operations of TABn and TAAn (by setting the TABnCTL0.TABnCE
(b) Setting of TABn register
(c) Setting of TMQOPn (TMQn option) register
(d) Setting of alternate function
bit and TAAnCTL0.TAAnCE bit to 0))
• Set the TAAnCTL1 register to 85H (set the tuning operation slave mode and free-running timer mode).
• Set the TAAnOPT0 register to 00H (select the compare register).
• Set an appropriate value to the TAAnCCR0 and TAAnCCR1 registers (set the default value for
• Set the TABnCTL1 register to 07H (set the master mode and 6-phase PWM output mode).
• Set an appropriate value to the TABnIOC0 register (set the output mode of TOBnT1 to TOBnT3).
• Clear the TABnIOC1 and TABnIOC2 registers to 00H (the TIBn0 to TIBn3, EVTBn, and TRGBn pins of
• Clear the TABnOPT0 register to 00H (select the compare register).
• Set an appropriate value to the TABnCCR0 to TABnCCR3 registers (set the default value for comparison
• Set the TABnCTL0 register to 0xH (set the TABnCE bit to 0 and the operating clock of TABn).
• Set an appropriate value to the TABnOPT1 and TABnOPT2 registers.
• Set an appropriate value to the TABnIOC3 register (set TOBnB1 to TOBnB3 in the output mode).
• Set an appropriate value to the TABnDTC register (set the default value for comparison for starting the
• Select the alternate function of the port by setting the port to the port control mode.
n = 0, 1
comparison for starting the operation).
However, set the TABnOL0 bit to 0 and the TABnOE0 bit to 1 (enable positive phase output). Unless
this setting is made, the crest interrupt (INTTBnCC0) and valley interrupt (INTTBnOV) do not occur.
Consequently, the conversion start trigger signal of A/D converters 0 and 1 is not correctly generated.
TABn are not used).
for starting the operation).
The operating clock of TABn set by the TABnCTL0 register is also supplied to TAAn, and the count
operation is performed at the same timing. The operating clock of TAAn set by the TAAnCTL0 register
is ignored.
operation).
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U18279EJ3V0UD
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