UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 851

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.5.13 Reception error
the reception error interrupt request signal (INTCBnRE) is generated when the next receive operation is ended before
the CBnRX register is read after the reception end interrupt request signal (INTCBnR) is generated, and the overrun
error flag (CBnSTR.CBnOVE) is set to 1.
if a reception error has occurred, the INTCBnRE signal is generated again upon the next reception end if the CBnRX
register is not read.
next receive data from the INTCBnR signal generation.
INTCBnRE signal
When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode,
Even if an overrun error has occurred, the previous receive data is lost since the CBnRX register is updated. Even
To avoid an overrun error, end reading the CBnRX register until one half clock before sampling the last bit of the
(1) Operation timing
(1) Start continuous transfer.
(2) End of the first transfer
(3) The CBnRX register cannot be read until one half-clock before the end of the second transfer.
(4) When an overrun error occurs and the reception error interrupt request signal (INTCBnRE) is generated,
Remark
SIBn pin capture
INTCBnR signal
CBnRX register
CBnRX register
Shift register
CBnOVE bit
read signal
SCKBn pin
the overrun error flag (CBnSTR.CBnOVE) is set (1). The receive data is overwritten.
SIBn pin
timing
n = 0 to 2
(1)
01H
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
02H
05H 0AH 15H 2AH 55H AAH 00H 01H 02H 05H 0AH 15H 2AH 55H
User’s Manual U18279EJ3V0UD
(2)
AAH
(3)
(4)
55H
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