UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 971

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
from on-chip peripheral I/O.
bit units; bits 5 to 0 (IFCn5 to IFCn0) can only be read or written in 8-bit units.
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt requests
The interrupt requests set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read or written in 1-
Reset sets these registers to 00H.
Cautions 1. Be sure to follow the steps below when changing the DTFRn register settings.
2. An interrupt request from an on-chip peripheral I/O input in the standby mode (IDLE or STOP
3. If the start factor of DMA transfer is changed using the IFCn5 to IFCn0 bits, be sure to set (0)
• When the values to be set to the IFCn5 to IFCn0 bits are not set to the IFCm5 to IFCm0 bits
• When the values to be set to the IFCn5 to IFCn0 bits are set to the IFCm5 to IFCm0 bits of
mode) is held pending as a DMA transfer start factor. The held DMA start factor is executed
after restoring to the normal operation mode.
the DFn bit by instruction immediately after.
of another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<5> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn) to
<6> Enable the DMAn operation (Enn and Emm bits = 1).
<1> Follow steps <3> to <5> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
<4> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn) to
<5> Enable the DMAn operation (Enn bit = 1).
<1> Follow steps <4> to <6> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Stop the DMAm operation of the channel where the same values are set to the IFCm5
<4> Change the DTFRn register settings. (Be sure to set the DFn bit = 0 and change the
to <5> when the Enn bit is set to 1.
settings in the 8-bit manipulation.)
0.
to <6> when the Enn bit is set to 1.
to IFCm0 bits as the values to be used to rewrite the IFCn5 to IFCn0 bits
(DCHCm.INITm bit = 1).
settings in the 8-bit manipulation.)
0.
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U18279EJ3V0UD
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