UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1019

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.5.3 Exception status flag (EP)
exception occurs. The EP flag is allocated to the PSW.
20.6 Exception Trap
V850E/IF3 and V850E/IG3, an illegal opcode trap (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
20.6.1 Illegal opcode definition
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
The EP flag is a status flag used to indicate that exception processing is in progress. This flag is set when an
This flag is set to 00000020H after reset.
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
Caution Since it is possible that this instruction may be assigned to an illegal opcode in the future, it is
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits (1).
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
The processing of the exception trap is shown below.
After reset: 00000020H
PSW
control.
recommended that it not be used.
×: Arbitrary
15
×
EP
×
0
1
×
×
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
11
×
Exception processing not in progress
Exception processing in progress
10
1
1
1
1
1
0
1
5
User’s Manual U18279EJ3V0UD
×
4
×
×
×
×
0
Exception processing status
31
×
×
×
×
27 26
×
0
1
NP EP
1
1
to
1
1
23 22
1
1
× × × × × ×
ID SAT CY OV
16
0
S
Z
1017