UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 770

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.5 Interrupt Request Signals
request signal, reception end interrupt request signal, transmission enable interrupt request signal, FIFO transmission
end interrupt request signal, and reception timeout interrupt request signal.
768
The following five types of interrupt requests are generated from UARTB.
The default priorities among these five types of interrupt requests is, from high to low, reception error interrupt
• Reception error interrupt request signal (INTUBTIRE)
• Reception end interrupt request signal (INTUBTIR)
• Transmission enable interrupt request signal (INTUBTIT)
• FIFO transmission end interrupt request signal (INTUBTIF)
• Reception timeout interrupt request signal (INTUBTITO)
(1) Reception error interrupt request signal (INTUBTIRE)
(a) Single mode
(b) FIFO mode
When reception is enabled, a reception error interrupt request signal is generated according to the logical
OR of the three types of reception errors (parity error, framing error, overrun error) explained for the
UBSTR register.
When reception is disabled, no reception error interrupt request signal is generated.
When reception is enabled, a reception error interrupt request signal is generated according to the logical
OR of the three types of reception errors (parity error, framing error, overflow error) explained for the
UBSTR register.
When reception is disabled, no reception error interrupt request signal is generated.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
Table 15-3. Generated Interrupts and Default Priorities
Reception error
Reception end
Transmission enable
FIFO transmission end
Reception timeout
User’s Manual U18279EJ3V0UD
Interrupt
Priority
1
2
3
4
5