UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 771

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Reception end interrupt request signal (INTUBTIR)
(3) Transmission enable interrupt request signal (INTUBTIT)
(4) FIFO transmission end interrupt request signal (INTUBTIF)
(a) Single mode
(b) FIFO mode
(a) Single mode
(b) FIFO mode
(a) Single mode
(b) FIFO mode
When reception is enabled, a reception end interrupt request signal is generated if data is shifted into the
receive shift register and stored in the UBRX register (if the receive data can be read).
When reception is disabled, no reception end interrupt request signal is generated.
When reception is enabled, a reception end interrupt request signal is generated if data is shifted into the
receive shift register and receive data of the number set as the trigger by the UBFIC2.UBRT3 to
UBFIC2.UBRT0 bits is transferred to receive FIFO (if receive data of the specified number can be read).
When reception is disabled, no reception end interrupt request signal is generated.
The transmission enable interrupt request signal is generated if transmit data of one frame, including 7 or
8 bits of characters, is shifted out from the transmit shift register and the UBTX register becomes empty
(if transmit data can be written).
The transmission enable interrupt request signal is generated if transmit data of the number set as the
trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits is transferred to the transmit shift register from
transmit FIFO (if transmit data of the specified number can be written).
Cannot be used.
The FIFO transmission end interrupt request signal is generated when no more data is in transmit FIFO
and the transmit shift register (when the FIFO and register become empty). After the FIFO transmission
end interrupt request signal has occurred, clear the interrupt request signal (INTUBTIT) held pending in
the pending mode (UBFIC0.UBITM bit = 0) by clearing the FIFO (UBFIC0.UBTFC bit = 1).
Caution If the FIFO transmission end interrupt request signal is generated (all transmit data are
not transmitted) because writing the next transmit data to transmit FIFO is delayed, do
not clear the FIFO.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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