UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 417

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(5) TMTm I/O control register 1 (TTmIOC1)
Note V850E/IG3 only
Cautions 1. Rewrite the TTmIS3 to TTmIS0 bits when the TTmCTL0.TTmCE bit = 0.
The TTmIOC1 register is an 8-bit register that controls the valid edge for the capture trigger input signals
(TITm0, TITm1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. The TTmIS3 and TTmIS2 bits are valid only in the free-running timer mode (only when the
V850E/IF3
V850E/IG3
m = 1
m = 0, 1
TTmIOC1
(The same value can be written when the TTmCE bit = 1.) If rewriting was mistakenly
performed, clear the TTmCE bit to 0 and then set the bits again.
TTmOPT0.TTmCCS1 bit = 1) and the pulse width measurement mode. In all other modes, a
capture operation is not possible.
The TTmIS1 and TTmIS0 bits are valid only in the free-running timer mode (only when the
TTmOPT0. TTmCCS0 bit = 1) and the pulse width measurement mode. In all other modes, a
capture operation is not possible.
After reset: 00H
TTmIS3
TTmIS1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
0
0
1
1
0
0
1
1
7
0
R/W
TTmIS2
TTmIS0
6
0
0
1
0
1
0
1
0
1
Address: TT0IOC1 FFFFF584H
User’s Manual U18279EJ3V0UD
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TITm1 pin) valid edge setting
Capture trigger input signal (TITm0 pin) valid edge setting
5
0
4
0
TTmIS3
3
Note
, TT1IOC1 FFFFF5C4H
TTmIS2
2
TTmIS1
1
TTmIS0
0
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