UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 670

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

trigger specified by the ADnTSEL.ADnTRGSEL11 and ADnTSEL.ADnTRGSEL10 bits is generated.
again.
668
12.4.9 Hardware trigger mode (normal operation mode)
The A/D converter waits for a trigger when the ADnSCM.ADnCE bit is set to 1, and starts A/D conversion when a
When conversion is started, the ADnSCM.ADnCS bit is set to 1 (conversion is in progress).
If the ADnSCM register is written during A/D conversion, the conversion is stopped and becomes trigger wait status
(1) Operation of 1-channel conversion
Remark
(1) AD0CE bit = 1 (enable)
(2) Trigger specified by AD0TSEL.AD0TRGSEL11
(3) Signal of ANI01 pin is A/D-converted
(4) Conversion result is stored in AD0CR1 register
Figure 12-18. Example of 1-Channel Conversion Operation (Hardware Trigger Mode): A/D Converter 0
AD0TSEL.AD0TRGSEL11 and
AD0TSEL.AD0TRGSEL10 bits
Remark
The signal of one analog input pin (ANInk) is converted once, using a signal specified by the
ADnTSEL.ADnTRGSEL11 and ADnTSEL.ADnTRGSEL10 bits as a trigger, and the result of conversion is
stored in one ADnCRk register. The ANInk pin and ADnCRk register correspond to each other on a one-to-
one basis.
Each time conversion has been completed, an A/Dn conversion end interrupt request signal (INTADn) is
generated. After completing the conversion, the converter waits for the trigger with the ADnSCM.ADnCE bit
set to 1.
This operation is suitable for an application where the result of A/D conversion should be read each time
conversion by one trigger has been completed.
and AD0TSEL.AD0TRGSEL10 bits is generated (7) Returns to (3) when the next trigger is input
ANInk
Analog Input Pin
This is an operation example when the AD0SCM.AD0PLM, AD0TRG1, and AD0TRG0 bits = 001,
AD0CTL0.AD0MD1 and AD0CTL0.AD0MD0 bits = 00, and AD0CHEN register = 0002H.
Trigger specified by
A/D converter 0: n = 0, k = 0 to 5
A/D converter 1: n = 1, k = 0 to 7
ADnCRk
A/D Conversion Result Register
CHAPTER 12 A/D CONVERTERS 0 AND 1
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
User’s Manual U18279EJ3V0UD
(5) AD0SCM.AD0CS bit = 0
(6) INTAD0 interrupt request signal is generated
(8) Set AD0CE bit to 0 to end (stop)
A/D converter 0
AD0CR0
AD0CR1
AD0CR2
AD0CR3
AD0CR4
AD0CR5