UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 17

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 18 BUS CONTROL FUNCTION.........................................................................................928
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)..................................................................959
17.8 Interrupt Request Signal (INTIIC) Generation Timing and Wait Control ...........................904
17.9 Address Match Detection Method.........................................................................................905
17.10 Error Detection........................................................................................................................905
17.11 Extension Code.......................................................................................................................905
17.12 Arbitration................................................................................................................................906
17.13 Wakeup Function ....................................................................................................................907
17.14 Communication Reservation .................................................................................................908
17.15 Cautions...................................................................................................................................912
17.16 Communication Operations...................................................................................................913
17.17 Timing of Data Communication.............................................................................................921
18.1 Features ...................................................................................................................................928
18.2 Bus Control Pins.....................................................................................................................929
18.3 Memory Block Function .........................................................................................................930
18.4 Bus Cycle Type Control Function .........................................................................................931
18.5 Bus Access..............................................................................................................................932
18.6 Wait Function ..........................................................................................................................941
18.7 Idle State Insertion Function..................................................................................................946
18.8 Bus Timing...............................................................................................................................948
18.9 Bus Priority Order...................................................................................................................958
18.10 Boundary Operation Conditions ...........................................................................................958
19.1 Features ...................................................................................................................................959
19.2 Configuration ..........................................................................................................................960
19.3 Control Registers....................................................................................................................961
17.7.4
17.7.5
17.7.6
17.14.1 When communication reservation function is enabled (IICF0.IICRSV0 bit = 0)......................... 908
17.14.2 When communication reservation function is disabled (IICF0.IICRSV0 bit = 1) ........................ 911
17.16.1 Master operation in single master system ................................................................................. 914
17.16.2 Master operation in multimaster system .................................................................................... 915
17.16.3 Slave operation ......................................................................................................................... 918
18.2.1
18.3.1
18.5.1
18.5.2
18.5.3
18.5.4
18.6.1
18.6.2
18.6.3
18.6.4
18.10.1 Program space .......................................................................................................................... 958
18.10.2 Data space ................................................................................................................................ 958
Operation without communication ............................................................................................. 894
Arbitration loss operation (operation as slave after arbitration loss) .......................................... 895
Operation when arbitration loss occurs (no communication after arbitration loss)..................... 897
Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access.................... 929
Chip select control function ....................................................................................................... 930
Number of access clocks .......................................................................................................... 932
Bus sizing function .................................................................................................................... 933
Endian function.......................................................................................................................... 934
Bus width................................................................................................................................... 934
Programmable wait function ...................................................................................................... 941
External wait function ................................................................................................................ 944
Relationship between programmable wait and external wait ..................................................... 944
Bus cycles in which wait function is valid................................................................................... 945
User’s Manual U18279EJ3V0UD
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