UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 674

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

by the ADnTSEL.ADnTRGSEL11 and ADnTSEL.ADnTRGSEL10 bits or selection trigger 2 specified by the
ADnTSEL.ADnTRGSEL21 and ADnTSEL.ADnTRGSEL20 bits is generated, the converter starts A/D conversion.
waits for the trigger again.
and ADnCHx.ADnTRGCHx6 to ADnCHx.ADnTRGCHx4 bits. Each time selection trigger x is generated, the analog
input pins specified by the ADnCHx.ADnTRGCHx2 to ADnCHx.ADnTRGCHx0 and ADnCHx.ADnTRGCHx6 to
ADnCHx.ADnTRGCHx4 bits are sequentially selected.
ADnTRGCH10 bits is converted when the trigger is generated for the first time. The result is stored in the A/Dn
conversion result extension buffer register 0 and an A/Dn conversion end interrupt request signal (INTADn) is
generated. When the trigger is generated the second time, the signal of the analog input pin specified by the
ADnTRGCH16 to ADnTRGCH14 bits is converted. The result is stored in the A/Dn conversion result extension buffer
register 0 and, at the same time, the first value stored in the A/Dn conversion result extension buffer register 0 is
stored in the A/Dn conversion result extension buffer register 1.
generated. For A/D conversion using selection trigger 1, up to three A/Dn conversion result extension buffer registers,
0 to 2, can be used. When selection load trigger 1 is later generated, the values of the A/Dn conversion result
extension buffer registers 0 to 2 are transferred to the ADnECR0 to ADnECR2 registers. After A/D conversion is
competed, the converter waits for the trigger with the ADnSCM.ADnCE bit remaining set to 1.
ADnTRGCH20 bits is converted when the trigger is generated for the first time, and the result is stored in the A/Dn
conversion end extension buffer register 3. Then an A/Dn conversion end interrupt request signal (INTADn) is
generated. When the trigger is generated the second time, the signal of the analog input pin specified by the
ADnTRGCH26 to ADnTRGCH24 bits is converted and the result is stored in the A/Dn conversion result extension
buffer register 4. At the same time, the value stored first in the A/Dn conversion result extension buffer register 3 is
stored in the A/Dn conversion result extension buffer register 4, and the INTADn interrupt request signal is generated.
When selection trigger 2 is used for A/D conversion, up to two A/Dn conversion result extension buffer registers, 3 and
4, can be used. When selection load trigger 2 is generated again, the values of the A/Dn conversion result extension
buffer registers 3 and 4 are transferred to and stored in the ADnECR3 and ADnECR4 registers. After A/D conversion
is completed, the converter waits for the trigger with the ADnCE bit remaining set to 1.
analog input signals should be monitored when a trigger is generated.
672
12.4.11 Extension buffer mode (extension operation mode)
When the ADnSCM.ADnCE bit is set to 1, the A/D converter waits for a trigger. When selection trigger 1 specified
When conversion is started, the ADnSCM.ADnCS bit is set to 1 (conversion is in progress).
If the ADnSCM register is written during A/D conversion operation, the conversion is stopped and the converter
The analog input pin for selection trigger x is specified by the ADnCHx.ADnTRGCHx2 to ADnCHx.ADnTRGCHx0
When selection trigger 1 is used, the signal of the analog input pin specified by the ADnTRGCH12 to
When selection trigger 2 is used, the signal of the analog input pin specified by the ADnTRGCH22 to
Therefore, the contents of the ADnECR0 to ADnECR4 registers can be saved to RAM all at once.
This operation is suitable for an application where there is little time to save the conversion result and two or more
Notes 1. Set by ADnCH1.ADnTRGCH12 to ADnCH1.ADnTRGCH10 bits
Selection trigger 1
Selection trigger 1
Selection trigger 1
Selection trigger 2
Selection trigger 2
Selection Trigger
2. Set by ADnCH1.ADnTRGCH16 to ADnCH1.ADnTRGCH14 bits
3. Set by ADnCH2.ADnTRGCH22 to ADnCH2.ADnTRGCH20 bits
4. Set by ADnCH2.ADnTRGCH26 to ADnCH2.ADnTRGCH24 bits
ANInx
ANIny
ANInx
ANIns
ANInt
Analog Input Pin
Note 4
Note 1
Note 2
Note 1
Note 3
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
ADnECR0 to ADnECR2
ADnECR0, ADnECR1
ADnECR0
ADnECR3, ADnECR4
ADnECR3
A/D Conversion Result Extension Register
Then the INTADn interrupt request signal is