UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 726

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

724
(2) UARTAn control register 1 (UAnCTL1)
(3) UARTAn control register 2 (UAnCTL2)
Note This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = UAnRXE bit = 0.
Remark
For details, see 14.7 (2) UARTAn control register 1 (UAnCTL1).
For details, see 14.7 (3) UARTAn control register 2 (UAnCTL2).
However, setting any or all of the UAnPWR, UAnTXE, and UAnRXE bits to 1 at the same time is
possible.
For details of parity, see 14.6.6 Parity types and operations.
UAnPS1
UAnDIR
UAnCL
UAnSL
If “reception with 0 parity” is selected during reception, a parity check is not performed.
Therefore, since the UAnSTR.UAnPE bit is not set, no error interrupt due to a parity
error is output.
Only the first bit of the receive data stop bits is checked, regardless of the value
of the UAnSL bit.
0
1
0
1
0
1
0
0
1
1
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Note
Note
Note
Note
UAnPS0
7 bits
8 bits
1 bit
2 bits
MSB-first transfer
LSB-first transfer
Specification of data character length of 1 frame of transmit/receive data
0
1
0
1
Note
Parity selection during transmission Parity selection during reception
No parity output
0 parity output
Odd parity output
Even parity output
Specification of length of stop bit for transmit data
User’s Manual U18279EJ3V0UD
Transfer direction selection
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
(2/2)