UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 781

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.3 Continuous transmission operation
• In single mode (UBFIC0.UBMOD bit = 0)
• If pending mode is specified (UBFIC0.UBITM bit = 0) in FIFO mode
• If pointer mode is specified (UBFIC0.UBITM bit = 1) in FIFO mode
In the single mode, the next data can be written to the UBTX register as soon as the transmit shift register has
started a shift operation. The timing of transfer can be identified by the transmission enable interrupt request
signal (INTUBTIT). By writing the next transmit data to the UBTX register via the INTUBTIT signal within one
data frame transmission period, data can be transmitted without an interval and an efficient communication
rate can be realized.
Caution Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission
If transmit data of at least the number set as the transmit trigger by UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and
16 bytes or less is written to transmit FIFO, transmission starts.
If the pending mode is specified in the FIFO mode, as many of the next transmit data as the number set as the
trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits can be written to transmit FIFO as soon as the transmit
shift register has started shifting the last data of the specified number of data. The timing of transfer can be
identified by the INTUBTIT signal. By writing as many of the next transmit data as the number set as the
trigger to transmit FIFO or writing the data to the FIFO within the transmission period of the data in transmit
FIFO via the INTUBTIT signal, data can be transmitted without an interval and an efficient communication rate
can be realized.
Caution Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission
If the pointer mode is specified in the FIFO mode, a INTUBTIT signal occurs and the next data can be written
to transmit FIFO as soon as the transmit shift register has started shifting the number of transmit data set as
the trigger. At this time, as many data as the number of empty bytes of transmit FIFO can be written by
referencing the UBFIS1 register. The timing of transfer can be identified by the INTUBTIT signal. By writing as
many of the next transmit data as the number specified as the trigger to transmit FIFO or writing the data to the
FIFO within the transmission period of the data in transmit FIFO via the INTUBTIT signal, data can be
transmitted without an interval and an efficient communication rate can be realized.
Caution Confirm that the UBSTR.UBTSF bit is 0 before executing initialization during transmission
processing. If initialization is executed while the UBTSF bit is 1, the transmit data is not
guaranteed.
processing (this can also be done by the FIFO transmission end interrupt request signal
(INTUBTIF)). If initialization is executed while the UBTSF bit is 1, the transmit data is not
guaranteed. To write transmit data to transmit FIFO by DMA, set the number of transmit data
specified as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits to 1 byte; otherwise the
operation will not be guaranteed.
processing (this can also be done by the FIFO transmission end interrupt request signal
(INTUBTIF)). If initialization is executed while the UBTSF bit is 1, the transmit data is not
guaranteed.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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