UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 753

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(12) UARTB transmit data register (UBTX)
(13) Timeout counter
(14) Sampling block
The transmit data register is a buffer for transmit data. The 8-bit × 1-stage UBTX register is used as this
buffer in the single mode. In the FIFO mode, the 8-bit × 16-stage transmit FIFO is used.
When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data register are transmitted
as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with
the MSB first, bits 7 to 1 of the transmit data register are transmitted as the transmit data from the MSB (bit 7)
with the LSB (bit 0) always being 0.
In the single mode, transmission is started by writing transmit data to the UBTX register while transmission is
enabled (UBCTL0.UBTXE bit = 1). When writing the transmit data to the UBTX register is enabled (when 1-
byte data is transferred from the UBTX register to the transmit shift register), a transmission enable interrupt
request signal (INTUBTIT) is generated.
In the FIFO mode, transmission is started by writing at least the number of transmit data set as the trigger by
the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and 16 bytes or less to transmit FIFO and then enabling
transmission (UBTXE bit = 1). When the number of transmit data set as the trigger by the UBFIC2.UBTT3 to
UBFIC2.UBTT0 bits have been transferred from transmit FIFO to the transmit shift register (transmit data of
the number set as the trigger can be written), a transmission enable interrupt request signal (INTUBTIT) is
generated. In the FIFO mode, a FIFO transmission enable interrupt request signal (INTUBTIF) is generated
when there is no more data in transmit FIFO and the transmit shift register (when FIFO and the register
become empty).
This counter is used to recognize that data exists (remains) in receive FIFO when the number of received
data does not reach the number set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits, and is valid
only in the FIFO mode.
If data is stored in receive FIFO when the next data does not come (start bit is not detected) after the next
data reception wait time specified by the UBFIC1.UBTC4 to UBFIC1.UBTC0 bits has elapsed after the stop
bit has been received, a reception timeout interrupt request signal (INTUBTITO) is generated.
This block samples the RXDB signal at the rising edge of the input clock (f
detected two times, output of the match detector changes, and the value is sampled as input data. Data of
less than one clock width is judged as noise and is not transmitted to the internal circuitry.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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). If the same sampling value is
751