UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 63

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.2 CPU Register Set
register set and a dedicated system register set. All the registers have a 32-bit width.
The registers of the V850E/IF3 and V850E/IG3 can be classified into two categories: a general-purpose program
For details, refer to V850E1 Architecture User’s Manual.
(1) Program register set
31
31
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30 (Element pointer (EP))
r31 (Link pointer (LP))
PC (Program counter)
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
Figure 3-1. CPU Register Set
CHAPTER 3 CPU FUNCTION
User’s Manual U18279EJ3V0UD
0
0
(2) System register set
31
EIPC (Status saving register during interrupt)
EIPSW (Status saving register during interrupt)
FEPC (Status saving register during NMI)
FEPSW (Status saving register during NMI)
ECR (Interrupt source register)
PSW (Program status word)
CTPC (Status saving register during CALLT execution)
CTPSW (Status saving register during CALLT execution)
DBPC (Status saving register during exception/debug trap)
DBPSW (Status saving register during exception/debug trap)
CTBP (CALLT base pointer)
0
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