UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 561

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note • V850E/IF3
• V850E/IG3
HZA0CTL0: TOB0OFF pin,
HZA1CTL0: TOB1OFF pin,
HZA2CTL0: ANI00/ANI05 pin,
HZA3CTL0: ANI10 to ANI12, ANI15 to ANI17 pins,
HZA3CTL1: ANI10 to ANI12, ANI15 to ANI17 pins
HZA0CTL0: TOB0OFF pin,
HZA1CTL0: TOB1OFF pin,
HZA2CTL0: ANI00/ANI05 pin,
HZA3CTL0: ANI10 to ANI12, ANI15 to ANI17 pins,
HZA3CTL1: ANI10 to ANI12, ANI15 to ANI17 pins
HZAyDCTn
HZAyDCCn
HZAyDCFn
• If an edge indicating abnormality is input to the external pin
• The HZAyDCTn bit is always 0 when it is read because it is a software-triggered
• The HZAyDCTn bit is invalid even if it is set to 1 when the HZAyDCEn bit = 0.
• Simultaneously setting the HZAyDCTn and HZAyDCCn bits to 1 is prohibited.
• Pins can function as output pins when the HZAyDCM bit = 0, regardless of the
• If an edge indicating abnormality is input to the external pin
• The HZAyDCCn bit is always 0 when it is read.
• The HZAyDCCn bit is invalid even if it is set to 1 when the HZAyDCEn bit = 0.
• Simultaneously setting the HZAyDCTn and HZAyDCCn bits to 1 is prohibited.
according to the setting of the HZAyDCNn and HZAyDCPn bits), the HZAyDCTn
bit is invalid even if it is set to 1.
bit.
status of the external pin
HZAyDCNn and HZAyDCPn bits) when the HZAyDCM bit = 1, the HZAyDCCn
bit is invalid even if it is set to 1.
0
1
0
1
0
1
No operation
Pins are made to go into a high-impedance state by software and the
HZAyDCFn bit is set to 1.
No operation
Pins that have gone into a high-impedance state are output-enabled by
software and the HZAyDCFn bit is cleared to 0.
Indicates that output of the pin is enabled.
• This bit is cleared to 0 when the HZAyDCEn bit = 0.
• This bit is cleared to 0 when the HZAyDCCn bit = 1.
Indicates that the pin goes into a high-impedance state.
• This bit is set to 1 when the HZAyDCTn bit = 1.
• This bit is set to 1 when an edge indicating abnormality is input to the
external pin
HZAyDCNn and HZAyDCPn bits).
CHAPTER 10 MOTOR CONTROL FUNCTION
Note
Note
(which is detected according to the setting of the
User’s Manual U18279EJ3V0UD
High-impedance output control clear bit
HZA0CTL1: TOA2OFF pin,
HZA2CTL1: ANI00/ANI05 pin,
HZA0CTL1: TOA2OFF pin,
HZA1CTL1: TOA3OFF pin,
HZA2CTL1: ANI00/ANI05 pin,
.
High-impedance output status flag
High-impedance output trigger bit
Note 2
Note
(which is set by the
(which is detected
(3/3)
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