UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 563

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(a) Setting procedure
(i) Setting of high-impedance control operation
(ii) Changing setting after enabling high-impedance control operation
(iii) Resuming output when pins are in high-impedance state
(iv) To make the pin to go into a high-impedance state by software
<1> Set the HZAyDCMn, HZAyDCNn, and HZAyDCPn bits.
<2> Set the HZAyDCEn bit to 1 (enable high-impedance control).
<1> Clear the HZAyDCEn bit to 0 (to stop the high-impedance control operation).
<2> Change the setting of the HZAyDCMn, HZAyDCNn, and HZAyDCPn bits.
<3> Set the HZAyDCEn bit to 1 (to enable the high-impedance control operation again).
If the HZAyDCMn bit is 1, set the HZAyDCCn bit to 1 to clear the high-impedance state after the valid
edge of the external pin
this bit is set while the input level of the external pin
<1> Set the HZAyDCCn bit to 1 (command signal to clear the high-impedance state).
<2> Read the HZAyDCFn bit and check the flag status.
<3> Return to <1> if the HZAyDCFn bit is 1. The input level of the external pin
The HZAyDCTn bit must be set to 1 by software to make the pin to go into a high-impedance state
while the input level of the external pin
the setting is not dependent upon the setting of the HZAyDCMn bit.
<1> Set the HZAyDCTn bit to 1 (high-impedance output command).
<2> Read the HZAyDCFn bit to check the flag status.
<3> Return to <1> if the HZAyDCFn bit is 0. The input level of the external pin
However, if the external pin
pin goes into a high-impedance state when the HZAyDCTn bit is set to 1.
Note • V850E/IF3
The pin can function as an output pin if the HZAyDCFn bit is 0.
The pin is in a high-impedance state if the HZAyDCFn bit is 1.
• V850E/IG3
HZA0CTL0: TOB0OFF pin,
HZA1CTL0: TOB1OFF pin,
HZA2CTL0: ANI00/ANI05 pin,
HZA3CTL0: ANI10 to ANI12, ANI15 to ANI17 pins,
HZA3CTL1: ANI10 to ANI12, ANI15 to ANI17 pins
HZA0CTL0: TOB0OFF pin,
HZA1CTL0: TOB1OFF pin,
HZA2CTL0: ANI00/ANI05 pin,
HZA3CTL0: ANI10 to ANI12, ANI15 to ANI17 pins,
HZA3CTL1: ANI10 to ANI12, ANI15 to ANI17 pins
CHAPTER 10 MOTOR CONTROL FUNCTION
Note
Note
is detected. However, the high-impedance state cannot be cleared unless
User’s Manual U18279EJ3V0UD
is not used with the HZAyDCPn bit and HZAyDCNn bit cleared to 0, the
Note
is inactive. The following procedure is an example in which
HZA0CTL1: TOA2OFF pin,
HZA2CTL1: ANI00/ANI05 pin,
HZA0CTL1: TOA2OFF pin,
HZA1CTL1: TOA3OFF pin,
HZA2CTL1: ANI00/ANI05 pin,
Note
is inactive.
Note
Note
must be checked.
must be checked.
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