UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 600

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

598
Transfer request
(4) Rewriting TABnOPT0.TABnCMS bit
<1> If the TABnCCR1 register is rewritten when the TABnCMS bit is 0, the transfer request signal is set.
<2> The register is not transferred because the TABnCMS bit is set to 1 and the transfer request signal is
<3> The transfer request signal is not set even if the TABnCCR1 register is written when the TABnCMS bit is 1.
<4> The transfer request signal is not set even if the TABnCCR1 register is written when the TABnCMS bit is 1,
<5> The transfer request signal is set if the TABnCCR1 register is written when the TABnCMS bit is 0.
<6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not
Remark
Write signal of
TABnCMS bit
CCR1 buffer
TABnCCR1
TABnCCR1
The TABnCMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten
during timer operation (when TABnCTL0.TABnCE bit = 1). However, the operation and caution illustrated in
Figure 10-36 are necessary.
If the TABnCCR1 register is written when the TABnCMS bit is set to 0, a transfer request signal (internal signal)
is set.
When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer
request signal is cleared. This transfer request signal is also cleared when the TABnCMS bit is set to 1.
If the TABnCMS bit is set to 1 in this status, the transfer request signal is cleared.
cleared.
so even if the TABnCMS bit is set to 0, transfer does not occur at the subsequent transfer timing.
Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared.
performed at the next transfer timing.
Transfer
counter
register
register
timing
signal
16-bit
n = 0, 1
0000H
i
CHAPTER 10 MOTOR CONTROL FUNCTION
Figure 10-36. Rewriting TABnCMS Bit
i
User’s Manual U18279EJ3V0UD
Clear
<1>
<2>
k
<3>
<4>
r
r
Clear
<5>
s
s
<6>