UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 658

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4 Operation
12.4.1 Basic operation
656
Cautions 1. A/D converters 0 and 1 are capable of simultaneous sampling of two circuits.
A/D conversion is executed by the following procedure.
(1) Select an input clock (f
(2) Set ADnSCM.ADnPS bit = 1.
(3) Wait for 1
(4) Select an analog input pin and operation mode, by using the ADnSCM
(5) In the A/D trigger mode and the A/D trigger polling mode, setting the ADnSCM.ADnCE bit to 1 starts A/D
(6) When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
(7) When sampling has been performed for a specific time, the sample & hold circuit enters the hold status, and
(8) Set bit 11 of the successive approximation register (SAR). The tap selector changes the level of the voltage
(9) The voltage generated by the voltage tap of the array is compared with the analog input voltage by a
of the operating clock to A/D converter n).
ADnTSEL, ADnCH1, ADnCH2, ADLTS1, and ADLTS2 registers (n = 0, 1). Number of A/D conversion clocks
and A/D conversion time are determined by the specification of the ADnCTC.ADnFR3 to ADnCTC.ADnFR0
bits.
Note Be sure to set bit 1 of the ADnSCM register to “1”.
conversion (n = 0, 1).
specification mode, and extension buffer mode, the A/D converter enters the trigger wait status.
sample & hold circuit. When the operational amplifier for input level amplification is used, the gain specified by
the OPnCTL0.OPnGA3 to OPnCTL0.OPnGA0 bits × the input voltage is sampled.
holds the input analog voltage until A/D conversion ends.
tap of the array to the reference voltage (1/2AV
comparator. If the analog input voltage is found to be greater than the reference voltage (1/2AV
result of comparison, the most significant bit (MSB) of the successive approximation register (SAR) remains
set. If the analog input voltage is less than the reference voltage (1/2AV
2. For details of operation setting, see 12.3 (1) A/D converter n scan mode register (ADnSCM).
This setting can be performed at the same time as other ADnSCM register bits.
μ
s or more after <2>.
AD01
If the ADnCE bit is set to 1 in the hardware trigger mode, conversion channel
) by using the ADnOCKS register and set the ADnOCKSEN bit to 1 (enable supply
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
REFPn
).
REFPn
Note
, ADnCTC, ADnCHEN, ADnCTL0,
), the MSB of the SAR is reset.
REFPn
) as a