UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 672

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

by the ADnTSEL.ADnTRGSEL11 and ADnTSEL.ADnTRGSEL10 bits is generated, the converter starts A/D
conversion.
waits for the trigger again.
ADnCH1.ADnTRGCH16 to ADnCH1.ADnTRGCH14 bits. Each time selection trigger 1 is generated, the analog input
pins specified by the ADnCH1.ADnTRGCH12 to ADnCH1.ADnTRGCH10 and ADnCH1.ADnTRGCH16 to
ADnCH1.ADnTRGCH14 bits are sequentially selected.
to 16 times), using selection trigger 1 as the trigger, and the result is stored in the ADnCRm register specified by the
ADnCHEN register. The conversion results are sequentially stored from ADnCR0.
specified by the ADnCHEN register, an A/Dn conversion end interrupt request signal (INTADn) is generated. After
A/D conversion is completed, the A/D converter waits for the trigger with the ADnSCM.ADnCE bit remaining set to 1.
670
12.4.10 Conversion channel specification mode (extension operation mode)
When the ADnSCM.ADnCE bit is set to 1, the A/D converter waits for a trigger. When selection trigger 1 specified
When conversion is started, the ADnSCM.ADnCS bit is set to 1 (conversion is in progress).
If the ADnSCM register is written during A/D conversion operation, the conversion is stopped and the converter
The analog input pin is specified by the ADnCH1.ADnTRGCH12 to ADnCH1.ADnTRGCH10 and
The signal of a specified analog input pin is converted the number of times specified by the ADnCHEN register (up
When the signal of the specified analog input pin has been converted the number of times (up to 16 times)
This operation is suitable for an application where two or more analog input signals should be monitored.
Notes 1. Set by ADnCH1.ADnTRGCH12 to ADnCH1.ADnTRGCH10 bits
Cautions 1. Be sure to set the hardware trigger mode as the conversion channel specification mode.
Remark
Selection trigger 1
Selection trigger 2
Selection Trigger
2. Set by ADnCH1.ADnTRGCH16 to ADnCH1.ADnTRGCH14 bits
3. Two or more times can be set by the ADnCHEN register.
2. Be sure to set the ADnCHEN register using the lower bits, justifying to the bottom. Any other
3. Setting of the ADnCH2 register is invalid.
4. The ADnECRa, ADnECRaH, ADnFLG, and ADnFLGB registers are not used. If these registers
5. Selection trigger 1 is ignored if it is generated during A/D conversion operation. The next
A/D converter 0: n = 0, k = 0 to 5, m = 0 to 15
A/D converter 1: n = 1, k = 0 to 7, m = 0 to 15
setting is prohibited.
are read, 0000H and 00H are read.
selection trigger 1 is accepted when a trigger is generated after completion of A/D
conversion (after generation of the INTADn signal).
ANInx
ANInx
ANInx
ANIny
ANIny
ANIny
Analog Input Pin
Note 1
Note 1
Note 1
Note 2
Note 2
Note 2
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
ADnCR0
ADnCRm
ADnCR0
ADnCRm
A/D Conversion Result Extension Register
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Note 3
Note 3
Note 3
Note 3