UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 630

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

628
(4) A/Dn conversion result registers 0 to 15, 0H to 15H (ADnCR0 to ADnCR15, ADnCR0H to ADnCR15H)
Remark
The ADnCRm and ADnCRmH registers are registers that hold the A/D conversion results in the A/D trigger
mode, A/D trigger polling mode, hardware trigger mode, or conversion channel specification mode. Sixteen of
these registers are provided per circuit, and two circuits are available. Each time A/D conversion ends, the
conversion result is loaded from the successive approximation register (SAR) and stored in the higher 12 bits
of the ADnCRm register. The lower 4 bits of these registers are always 0 when read.
The higher 8 bits of A/D conversion result are read to the ADnCRmH register.
These registers can only be read in 16-bit or 8-bit units. When the A/D conversion results are read in 16-bit
units, the ADnCRm register is specified, and when the higher 8 bits are read, the ADnCRmH register is
specified.
Reset sets these registers to 0000H.
While the result of A/D conversion is stored in the ADnCRm register, a read access to the same
register is held pending. The pending read access is executed after the A/D conversion result is
stored. Similarly, storing the result of A/D conversion in the ADnCRm register is held pending while
a read access to that register is made. The pending A/D conversion result storing processing is
executed after completion of the read access.
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD