UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 1018

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UPD70F3451GC-UBT-A

Manufacturer Part Number
UPD70F3451GC-UBT-A
Description
MCU 32BIT 128KB FLASH 80LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3451GC-UBT-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
44
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 4x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3451GC-UBT-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
20.5.2 Restore
address of the restored PC.
1016
Execution is restored from software exception processing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1.
<2> Transfers control to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Caution When the PSW.EP and PSW.NP bits are changed by the LDSR instruction during software
Remark
exception processing, in order to restore the PC and PSW correctly during restoring by the
RETI instruction, it is necessary to set the EP bit back to 1 and clear the NP bit to 0 using the
LDSR instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 20-9. RETI Instruction Processing
User’s Manual U18279EJ3V0UD

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