UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 189

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Internal reset signal
(2) Reset input with power on
PLL output clock
<1> The oscillator continues operating during the reset period.
<2> When the fixed oscillation stabilization time that elapses after the reset signal is released expires, PLL
<3> PLL is locked when counting of the lockup time is over. The OST counter is initialized to 00H.
<4> When the lockup time expires, the CPU releases the reset signal and operates in the clock-through
Note RESET pin input, reset signal (WDTRES) generation by the watchdog timer, reset signal (LVIRES)
Cautions 1. The clock generated by the oscillator continues operating during a reset.
OST counter
V
Reset
DD0
PLL stops during the reset period and fixed oscillation stabilization time.
stop is released, and counting the lockup time starts.
mode (f
generation by the low-voltage detector (LVI), or reset signal (POCRES) generation by the power-on-
clear circuit (POC)
, V
Note
f
DD1
CPU
X1
2. To avoid malfunction due to noise, do not change the division ratio of the CPU
X
H
). The CPU operation clock (f
After the reset signal is released, a specific wait time (fixed oscillation stabilization
time) elapses.
operation clock (f
changing the division ratio, be sure to select the PLL mode.
00H (initialization)
<1>
CPU
CHAPTER 5 CLOCK GENERATOR
Fixed oscillation stabilization
time of clock from oscillator
) by using the PCC register before setting the PLL mode. Before
User’s Manual U18279EJ3V0UD
1.024 ms (at 8 MHz)
CPU
) is f
XX
/8. The PLL mode can be set by software.
1.024 ms (at 8 MHz)
PLL lockup time
<2>
f
XX
/8 of clock-through mode after reset
<3>
PLL output stabilized
00H
<4>
187