UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 760

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

758
(4) UARTB transmit data register (UBTX)
The UBTX register is used to set transmit data. It functions as the 8-bit × 1-stage UBTX register, in the single
mode (UBFIC0.UBMOD bit = 0), and as the 8-bit × 16-stage transmit FIFO in the FIFO mode
(UBFIC0.UBMOD bit = 1).
In the single mode, transmission is started by writing transmit data to the UBTX register when transmission is
enabled (UBCTL0.UBTXE bit = 1). When data can be written to the UBTX register (when 1 byte of data is
transferred from the UBTX register to the transmit shift register), a transmission enable interrupt request
signal (INTUBTIT) is generated.
In the FIFO mode, transmission is started by enabling transmission (UBTXE bit = 1) after writing at least the
number of transmit data set as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and 16 bytes or less
to transmit FIFO.
UBFIC2.UBTT0 bits have been transferred from transmit FIFO to the transmit shift register (transmit data of
the number set as the trigger can be written to transmit FIFO), a transmission enable interrupt request signal
(INTUBTIT) is generated. In the FIFO mode, a FIFO transmission enable interrupt request signal (INTUBTIF)
is generated when there is no more data in transmit FIFO and the transmit shift register (when the FIFO and
register become empty).
For the generation timing of the interrupt, see 15.5 Interrupt Request Signals.
When 7-bit length data is transmitted with the LSB first, bits 6 to 0 of the transmit data register are transmitted
as the transmit data from the LSB (bit 0) with the MSB (bit 7) always being 0. When data is transmitted with
the MSB first, bits 7 to 1 of the transmit data register are transmitted as the transmit data from the MSB (bit 7)
with the LSB (bit 0) always being 0.
This register is write-only in 8-bit units. Data is written to the transmit data register.
Reset sets this register to FFH.
UBTX
After reset: FFH
UBTD7
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
7
When the number of transmit data set as the trigger by the UBFIC2.UBTT3 to
UBTD6
W
6
Address: FFFFFA48H
UBTD5
User’s Manual U18279EJ3V0UD
5
UBTD4
4
UBTD3
3
UBTD2
2
UBTD1
1
UBTD0
0