UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 374

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

372
<1> Count operation start flow
<2> TABnCCR0 to TABnCCR3 register
<3> TABnCCR0 register setting change flow
Setting of TABnCCR0 register
Setting of TABnCCR1 register
Setting of TABnCCR0, TABnCCR2,
TABnCCR0 to TABnCCR1
setting change flow
Register initial setting
and TABnCCR3 registers
TABnCCR1 register
TABnCTL1 register,
TABnIOC0 register,
TABnIOC2 register,
TABnCTL0 register
TABnCE bit = 1
TABnCKS2 bits)
(TABnCKS0 to
Remark
START
registers
n = 0, 1
a = 0 to 3
Figure 7-31. Software Processing Flow in PWM Output Mode (2/2)
Initial setting of these
registers is performed
before setting the
TABnCE bit to 1.
The TABnCKS0 to
TABnCKS2 bits can be
set at the same time
as when counting is
enabled (TABnCE bit = 1).
Writing of the TABnCCR1
register must be performed
after writing the TABnCCR0,
TABnCCR2, and TABnCCR3
registers.
When the counter is cleared
after setting, the value
of the TABnCCRa register is
transferred to the CCRa buffer
registers.
Writing same value (same as
preset value of the TABnCCR1
register) to the TABnCCR1
register is necessary only
when the set cycle is changed.
When the counter is
cleared after setting, the
value of the TABnCCRa
register is transferred to
the CCRa buffer register.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
User’s Manual U18279EJ3V0UD
<4> TABnCCR1 to TABnCCR3 register
<6> TABnCCR1 register setting change flow
<7> Count operation stop flow
<5> TABnCCR2, TABnCCR3 register
Setting of TABnCCR1 register
Setting of TABnCCR1 register
Setting of TABnCCR1 register
Setting of TABnCCR2 and
Setting of TABnCCR2 and
setting change flow
TABnCCR3 registers
TABnCCR3 registers
setting change flow
TABnCE bit = 0
STOP
Only writing of the TABnCCR1
register must be performed
when the set duty factor is only
changed after writing the
TABnCCR2 and TABnCCR3
registers.
When the counter is cleared after
setting, the value of the
TABnCCRa register is transferred
to the CCRa buffer register.
Writing same value (same as
preset value of the TABnCCR1
register) to the TABnCCR1
register is necessary only when
the set duty factor of TOBn2
and TOBn3 pin outputs is changed.
When the counter is cleared after
setting, the value of the
TABnCCRa register is transferred
to the CCRa buffer register.
Only writing of the TABnCCR1
register must be performed when
the set duty factor of TOBn1
pin is only changed.
When counter is cleared after
setting, the value of the TABnCCRa
register is transferred to the CCRa
buffer register.
Counting is stopped.