UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 637

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ADnTRGCH16 to ADnTRGCH14 bits
ADnTRGCH12 to ADnTRGCH10 bits
ADnTRGCH16 to ADnTRGCH14 bits
ADnTRGCH12 to ADnTRGCH10 bits
Setting the ADnCH1 register is enabled when a conversion operation is enabled (ADnSCM.ADnCE bit = 1) in
the conversion channel specification mode or extension buffer mode. When the first selection trigger 1 is
generated after the conversion operation is enabled (ADnCE bit = 1), the analog input pin specified by the
ADnTRGCH12 to ADnTRGCH10 bits is selected and A/D conversion is executed. When the next selection
trigger 1 is later generated, the analog input pin specified by the ADnTRGCH16 to ADnTRGCH14 bits is
selected and A/D conversion is executed. After that, the analog input pins are alternately selected for output
each time selection trigger 1 is generated.
If an error occurs (when selection trigger 1 is generated during A/D conversion), the analog input pin specified
by the ADnTRGCH12 to ADnTRGCH10 bits and the analog input pin specified by the ADnTRGCH16 to
ADnTRGCH14 bits are alternately selected, but the selected analog input pin is not changed because A/D
conversion is in progress.
Selection of analog input pin
Selection of analog input pin
A/D conversion status
Selection trigger 1
Selection trigger 1
Figure 12-8. ADnCH1 Register Operation In Case of Error
Figure 12-7. ADnCH1 Register Operation
CHAPTER 12 A/D CONVERTERS 0 AND 1
During A/D conversion
User’s Manual U18279EJ3V0UD
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100
Error occurs
During A/D conversion
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101
100
101
101
100
During A/D conversion
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100
During A/D conversion
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