UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 669

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 12-17. Example of Multiple Channel Conversion Operation (A/D Trigger Polling Mode): A/D Converter 0
(2) Operation of multiple channel conversion
Remark
(1) AD0CE bit = 1 (enable)
(2) Signal of ANI01 pin is A/D-converted
(3) Conversion result is stored in AD0CR1 register
(4) Signal of ANI03 pin is A/D-converted
(5) Conversion result is stored in AD0CR3 register
(6) Signal of ANI05 pin is A/D-converted
Note Two or more can be specified by the ADnCHEN register.
Remark
The signals of two or more analog input pins specified by the ADnCHEN register are converted sequentially
starting from the pin with the lowest number. The result of conversion is stored in the ADnCRk register
corresponding to the analog input pin.
When conversion of the signals of all the specified analog input pins is completed, an A/Dn conversion end
interrupt request signal (INTADn) is generated. A/D conversion is repeated until the ADnSCM.ADnCE bit is
set to 0. The conversion operation is stopped when the ADnCE bit is cleared to 0.
It is not necessary to set the ADnCE bit to restart the conversion operation in the A/D trigger polling mode.
This operation is suitable for an application where the A/D conversion value is always read.
ANInk
ANInk
Analog Input Pin
|
AD0SCM
This is an operation example when the AD0SCM.AD0PLM, AD0TRG1, and AD0TRG0 bits = 100,
AD0CTL0.AD0MD1 and AD0CTL0.AD0MD0 bits = 00, and AD0CHEN register = 002AH.
Note
Note
However, A/D conversion is sequentially executed starting from the pin with the lowest number.
A/D converter 0: n = 0, k = 0 to 5
A/D converter 1: n = 1, k = 0 to 7
ADnCRk
ADnCRk
A/D Conversion Result Register
|
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
(7) Conversion result is stored in AD0CR5 register
(8) AD0SCM.AD0CS bit = 0
(9) INTAD0 interrupt request signal is generated
(10) Return to (2)
(11) Set AD0CE bit to 0 to end (stop)
A/D converter 0
AD0CR0
AD0CR1
AD0CR2
AD0CR3
AD0CR4
AD0CR5
667