UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 310

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

308
Note Writing to the TABnCCR1 register is the trigger.
Remark
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
(a) Function as compare register
(b) Function as capture register
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
The TABnCCR2 register can be rewritten even when the TABnCTL0.TABnCE bit = 1.
The set value of the TABnCCR2 register is transferred to the CCR2 buffer register. When the value of the
16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal
(INTTBnCC2) is generated. If TOBn2 pin output is enabled at this time, the output of the TOBn2 pin is
inverted.
The compare register is not cleared by setting the TABnCTL0.TABnCE bit to 0.
When the TABnCCR2 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TABnCCR2 register if the valid edge of the capture trigger input pin
(TIBn2 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TABnCCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIBn2 pin) is detected.
Even if the capture operation and reading the TABnCCR2 register conflict, the correct value of the
TABnCCR2 register can be read.
The capture register is cleared by setting the TABnCTL0.TABnCE bit to 0.
For anytime write and batch write, see 7.6 (2) Anytime write and batch write.
Operation Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U18279EJ3V0UD
Capture/Compare Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note
Note