UPD70F3451GC-UBT-A Renesas Electronics America, UPD70F3451GC-UBT-A Datasheet - Page 422

• Manufacturer Part Number: UPD70F3451GC-UBT-A
• Description: MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3451GC-UBT-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

420
(9) TMTm option register 1 (TTmOPT1)
Note V850E/IG3 only
The TTmOPT1 register is an 8-bit register that detects the overflow, underflow, and count-up/down operation of
the encoder count function.
The TTmOPT1 register is valid only in the encoder compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
This register can be rewritten even when the TTmCTL0.TTmCE bit = 1.
V850E/IF3
V850E/IG3
TTmOPT1
m = 1
m = 0, 1
After reset: 00H
Reset (0)
TTmEUF
• The TTmEUF bit is set to 1 when 16-bit counter underflows from 0000H to FFFFH
• When the TTmCTL2.TTmLDE bit = 1, TTmEUF bit is set to 1 when value of 16-bit
• Overflow interrupt request signal (INTTTIOVm) is generated as soon as the
• The TTmEUF bit is not cleared to 0 even if the TTmEUF bit or TTmOPT1 register
• Status of the TTmEUF bit is retained even if the TTmCTL0.TTmCE bit is cleared
• Before clearing the TTmEUF bit to 0 after the INTTTIOVm signal is generated, be
• The TTmEUF bit can be read or written, but it cannot be set to 1 by software.
Set (1)
in encoder compare mode.
counter is changed from 0000H to set value of the TTmCCR0 register.
TTmEUF bit is set to 1.
is read when the TTmEUF bit = 1.
to 0 when the TTmCTL2.TTmECC bit = 1.
sure to confirm (read) that the TTmEUF bit is set to 1.
Setting this bit to 1 does not affect operation of TMTm.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
0
7
R/W
Underflow occurs.
Cleared by writing to TTmEUF bit or when TTmCTL0.TTmCE bit = 0
6
0
Address: TT0OPT1 FFFFF588H
User’s Manual U18279EJ3V0UD
0
5
TMTm underflow detection flag
4
0
3
0
Note
TTmEUF TTmEOF TTmESF
, TT1OPT1 FFFFF5C8H
<2>
<1>
<0>
(1/2)